Toshiba today showed first 300mm wafer based on 32nm manufacturing technology at International Nanotechnology Exhibition and Conference. Each chip made using 32nm process will have 32-gigabit (4GB) capacity and it will use the 3-bit per cell technology that Toshiba developed in collaboration with SanDisk.
Toshiba notes that they didn’t make any significant changes to the design from its earlier 43nm wafers, which used a similar floating gate structure to manage the flow of power. Toshiba also revealed their plan to use 20-30nm process technology in late 2010 or 2011. Though with further decrease in size the company will have to use nitride trap in place of floating gate structure to manage the flow of power.
Volume production of 32nm based NAND chips will start in September this year with products based on new flash memory coming to market in Q4 2009.
[Via MacNN]