Today at Intel Developer Forum in San Francisco, Intel’s CEO Paul Otellini showed world’s first 300mm wafer built using next-generation 32nm process technology. The 32nm test chips incorporate logic and memory to house more than 1.9 billion transistors. The 32nm process also uses second generation high-k and metal gate transistor technology. Paul Otellini said “ Chips based on its upcoming 32nm technology are due out in2009 and will include transistors so small that more than 4 million of them could fit on the period at the end of this sentence.” Using 32nm process will increase performance and decreases power requirement.